Field of the Disclosure
Embodiments of the present disclosure generally relate to a method for controlled switching of a magnetoresistive random-access memory (MRAM) device, and more particularly to control switching of an MRAM device in real time.
Description of the Related Art
Magnetoresistive random-access memory (MRAM) is a non-volatile random-access memory technology. Unlike conventional RAM, data in MRAM devices are not stored as electric charge or current flows. Rather, data is stored by magnetic storage elements. MRAM devices include cells or elements having a magnetically hard layer (i.e., a “reference” layer) and a magnetically soft layer (i.e., the “free” layer). Writing to MRAM is performed by passing current through current leads that are formed on either side of each memory element in order to create a local induced magnetic field, which sets the direction of the soft layer magnetization. Significant problems arise when scaling these devices to high densities. Particularly, disturbances to neighboring cells or elements can occur during wiring, which in turn may cause a neighboring cell to be erroneously written.
Spin transfer torque (STT) MRAM devices are similar to conventional MRAM devices except that the current paths pass through the magnetic layers of each memory element. A free layer is one of the magnetic layers in the MRAM device. The orientation of the free layer is changed by the action of angular momentum transfer from a spin-polarized current created by passing current through another magnetic layer.
Spin orbit torque (SOT) MRAM devices are similar to STT-MRAM devices except that the read and write paths are independent. Because the read and write paths in a SOT-MRAM device are independent, the current densities passing through SOT-MRAM devices can be significantly lower than in STT-MRAM devices, which may result in better device endurance.
MRAM devices contain arrays of MRAM cells. There are a number of different architectures in which the cells can be arranged. In one architecture, a two terminal MRAM cell is arranged in a 1T-1R format where 1T refers to select transistor and 1R refers to the MRAM device. The array is built up with a set of electrically conducting lines, called bit-lines, source-lines, and word-lines. One side of a set of MRAM cells are connected to a bit-line. The other side of a set of MRAM cells is connected to a source-line. The gates of the transistors are connected to word-lines. The MRAM device is connected in series with the source and drain of the transistor.
A read sense amplifier is connected to the bit-lines and measures the voltage on the bit-line for reading while the write driver is off. A write sense amplifier is used to measure the voltage on or the current through the MRAM device while the write current is on. In some embodiments the read and write amplifiers may use some of the same circuitry.
When the select transistor is turned on, a voltage or current is applied to the MRAM cell. The resistance of the MRAM device depends upon the magnetic state of the MRAM. If the voltage or current is at a sufficiently low level, the magnetic state of the MRAM cell will be unaffected and that voltage or current can be used to read the state of the MRAM device without reprogramming or rewriting it. If the read voltage or read current is sent to the MRAM device, the read voltage or read current is affected by the resistance of the MRAM device. If the MRAM device is in one magnetic state the read voltage or read current will have one value and will cause the sense amplifier to produce one voltage. If the MRAM device is in a second magnetic state, its resistance will be a second value and the read voltage produced by the sense amplifier will be a different value. The sense amplifier produces a voltage related to the resistance of the MRAM device. In practice there is noise in the system so the signal produced by the sense amplifier from a particular MRAM cell will fluctuate due to that noise. In practice it is not possible to make each MRAM cell identical. Therefore, the resistance of a set of MRAM cells will be different, even if they are in the same state. The resistance of that set of cells in a different magnetic state will also differ from one another. But for a particular MRAM device the resistance of different states of that MRAM device will be different and can be distinguished.
MRAM devices contain elements, or cells, that switch the MRAM device between a first state and a second state. With current methods for switching an MRAM device from a first state to a second state, write failure occurs due to several possible mechanisms, including distributions of write currents in an ensemble of bits or nondeterministic switching due to the specific nature of the write method used. In the former case, writing may be mostly successful but once in a while a write error will occur. The latter case, which is typically referred to as probabilistic switching, makes writing strongly dependent on certain parameters, such as the width of the write voltage/current pulse. While write errors can be mitigated by adding error correction code (ECC), this method adds complexity and cost to the building of memory chips. The use of ECC requires the final state be measured and the write procedure repeated if the device is not in the desired state. This method significantly degrades memory latency because it is time consuming and is not optimal as there is still a non-zero probability for the device to end up in the wrong state even after a large number of tries.
As high density nonvolatile memory devices become increasingly more popular in diverse applications, there is a continual need for improved MRAM devices. Thus, what is needed is an improved method of controlled switching an MRAM device.